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readme.markdown

VHDL code for TRNG designs

AIS-20/31 Compliant TRNG Cores Suitable for FPGA devices

Acknowledgements

HECTOR logo

This work has received funding from the European Union's Horizon 2020 research
and innovation programme in the
framework of the project HECTOR (Hardware Enabled Crypto and Randomness) under
grant agreement No 644052.