Commit 1d0326e5a3dd444e4df0ffe395ab7aee2e7cc65c

Authored by Brice Colombier
1 parent ee1823b28b
Exists in master

Better README

Showing 1 changed file with 7 additions and 7 deletions

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4 4 These Python scripts can convert combinational netlist files to directed acyclic graphs in the [igraph](http://igraph.org/python/) format.
5 5  
6 6 So far it handles the following netlist formats:
7   -- bench: ISCAS'85 and ITC'99 netlists format
8   -- BLIF: Berkeley Logic Interchange Format
9   -- SLIF: Stanford Logic Interchange Format
10   -- EDIF: Electronic Design Interchange Format
11   -- VHDL (dataflow and structural)
12   -- Verilog (dataflow and structural)
13   -- Xilinx EDIF
  7 +- **bench**: ISCAS'85 and ITC'99 netlists format
  8 +- **BLIF**: Berkeley Logic Interchange Format
  9 +- **SLIF**: Stanford Logic Interchange Format
  10 +- **EDIF**: Electronic Design Interchange Format
  11 +- **VHDL** (dataflow and structural)
  12 +- **Verilog** (dataflow and structural)
  13 +- **Xilinx EDIF**: Netlist mapped to Xilinx LUTs