Commit 6ecd6a48d0f807524c9dfc69c5710b01a9db1ac7

Authored by Brice Colombier
1 parent 56463a5f12
Exists in master

Decoder working, lacks unit testing

Showing 2 changed files with 166 additions and 77 deletions

AW_decoder/AW_decoder.vhd View file @ 6ecd6a4
... ... @@ -5,7 +5,7 @@
5 5  
6 6 PORT (
7 7 formatted_AW : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
8   - AW : OUT STD_LOGIC_VECTOR(8 DOWNTO 0));
  8 + AW : OUT STD_LOGIC_VECTOR(15 DOWNTO 0));
9 9  
10 10 END ENTITY AW_decoder;
11 11  
... ... @@ -16,8 +16,34 @@
16 16  
17 17 BEGIN
18 18  
19   - -- Formatted AW: 10101110, MSB first
20   - -- AW: 1010 1010, MSB first
  19 + -- Formatted AW: 01010100
  20 + -- AW: 11111110 10011000
  21 +
  22 + -- Lock AND
  23 + locking_1 <= formatted_AW(4) AND formatted_AW(6);
  24 + AW(12) <= locking_1;
  25 + AW(9) <= locking_1;
  26 + AW(10) <= locking_1;
  27 + AW(11) <= locking_1;
  28 + AW(15) <= locking_1;
  29 + AW(14) <= locking_1;
  30 + AW(13) <= locking_1;
  31 +
  32 + -- Lock OR
  33 + locking_0 <= formatted_AW(7) OR formatted_AW(5);
  34 + AW(8) <= locking_0;
  35 +
  36 + -- Mask ANDs
  37 + AW(7) <= formatted_AW(2)
  38 + AW(3) <= formatted_AW(2)
  39 + AW(4) <= formatted_AW(2)
  40 +
  41 + -- Mask ORs
  42 + AW(5) <= formatted_AW(1);
  43 + AW(2) <= formatted_AW(1);
  44 + AW(1) <= formatted_AW(3);
  45 + AW(0) <= formatted_AW(3);
  46 + AW(6) <= formatted_AW(0);
21 47  
22 48 END ARCHITECTURE rtl;
AW_decoder/gen_AW_decoder.py View file @ 6ecd6a4
... ... @@ -74,9 +74,59 @@
74 74 assoc_mask_ORs = [(x[0][0], x[1]) if (type(x[0]) == list and len(x[0]) == 1) else x for x in assoc_mask_ORs]
75 75 return assoc_mask_ORs
76 76  
77   -def gen_AW_decoder (AW, width_formatted_AW, locking=True, masking=True):
  77 +def write_masking_part_to_file(vhd_file, assoc_mask_ANDs, assoc_mask_ORs):
  78 + vhd_file.write("\n -- Mask ANDs\n")
  79 + for (inputs, outputs) in assoc_mask_ANDs:
  80 + if type(inputs) == int and type(outputs) == int:
  81 + vhd_file.write(" AW("+str(outputs)+") <= formatted_AW("+str(inputs)+");\n")
  82 + elif type(inputs) == int and type(outputs) == list:
  83 + for output in outputs:
  84 + vhd_file.write(" AW("+str(output)+") <= formatted_AW("+str(inputs)+")\n")
  85 + elif type(inputs) == list and type(outputs) == int:
  86 + vhd_file.write(" AW("+str(outputs)+") <= "+" AND ".join(["formatted_AW("+str(i)+")" for i in inputs])+";\n")
  87 + vhd_file.write("\n -- Mask ORs\n")
  88 + for (inputs, outputs) in assoc_mask_ORs:
  89 + if type(inputs) == int and type(outputs) == int:
  90 + vhd_file.write(" AW("+str(outputs)+") <= formatted_AW("+str(inputs)+");\n")
  91 + elif type(inputs) == int and type(outputs) == list:
  92 + for output in outputs:
  93 + vhd_file.write(" AW("+str(output)+") <= formatted_AW("+str(inputs)+");\n")
  94 + elif type(inputs) == list and type(outputs) == int:
  95 + vhd_file.write(" AW("+str(outputs)+") <= "+" OR ".join(["formatted_AW("+str(i)+")" for i in inputs])+";\n")
  96 +
  97 +def write_locking_part_to_file(vhd_file, assoc_lock_ANDs, assoc_lock_ORs):
  98 + vhd_file.write("\n -- Lock AND\n")
  99 + for (inputs, outputs) in assoc_lock_ANDs:
  100 + vhd_file.write(" locking_1 <= "+" AND ".join(["formatted_AW("+str(i)+")" for i in inputs])+";\n")
  101 + for output in outputs:
  102 + vhd_file.write(" AW("+str(output)+") <= locking_1;\n")
  103 + vhd_file.write("\n -- Lock OR\n")
  104 + for (inputs, outputs) in assoc_lock_ORs:
  105 + vhd_file.write(" locking_0 <= "+" OR ".join(["formatted_AW("+str(i)+")" for i in inputs])+";\n")
  106 + for output in outputs:
  107 + vhd_file.write(" AW("+str(output)+") <= locking_0;\n")
  108 +
  109 +def write_header(vhd_file, locking, width_formatted_AW, len_AW):
  110 + vhd_file.write("LIBRARY ieee;\n")
  111 + vhd_file.write("USE ieee.std_logic_1164.ALL;\n\n")
  112 + # Entity
  113 + vhd_file.write("ENTITY AW_decoder IS\n\n")
  114 + vhd_file.write(" PORT (\n")
  115 + vhd_file.write(" formatted_AW : IN STD_LOGIC_VECTOR("+str(width_formatted_AW-1)+" DOWNTO 0);\n")
  116 + vhd_file.write(" AW : OUT STD_LOGIC_VECTOR("+str(len_AW-1)+" DOWNTO 0));\n\n")
  117 + vhd_file.write("END ENTITY AW_decoder;\n\n")
  118 + # Architecture
  119 + vhd_file.write("ARCHITECTURE rtl OF AW_decoder IS\n\n")
  120 + if locking:
  121 + vhd_file.write(" SIGNAL locking_0 IS STD_LOGIC;\n")
  122 + vhd_file.write(" SIGNAL locking_1 IS STD_LOGIC;\n\n")
  123 + vhd_file.write("BEGIN\n\n")
  124 +
  125 +
  126 +def gen_AW_decoder (AW, width_formatted_AW, locking=True, masking=True, formatted_AW=""):
78 127 """Generates a decoder for the Activation Word
79 128  
  129 + AW: activation word, provided MSB first
80 130 width_formatted_AW: width of the formatted AW
81 131 """
82 132  
83 133  
84 134  
... ... @@ -103,83 +153,95 @@
103 153  
104 154 with open("AW_decoder.vhd", "w") as vhd_file:
105 155 # Header
106   - vhd_file.write("LIBRARY ieee;\n")
107   - vhd_file.write("USE ieee.std_logic_1164.ALL;\n\n")
108   - # Entity
109   - vhd_file.write("ENTITY AW_decoder IS\n\n")
110   - vhd_file.write(" PORT (\n")
111   - vhd_file.write(" formatted_AW : IN STD_LOGIC_VECTOR("+str(width_formatted_AW-1)+" DOWNTO 0);\n")
112   - vhd_file.write(" AW : OUT STD_LOGIC_VECTOR("+str(len(AW)-1)+" DOWNTO 0));\n\n")
113   - vhd_file.write("END ENTITY AW_decoder;\n\n")
114   - # Architecture
115   - vhd_file.write("ARCHITECTURE rtl OF AW_decoder IS\n\n")
116   - if locking:
117   - vhd_file.write(" SIGNAL locking_0 IS STD_LOGIC;\n")
118   - vhd_file.write(" SIGNAL locking_1 IS STD_LOGIC;\n\n")
119   - vhd_file.write("BEGIN\n\n")
120   - # Computation
121   - formatted_AW = ''.join([str(int(2*rd.random())) for i in xrange(width_formatted_AW)])
122   - print "Formatted AW:", formatted_AW
123   - print " AW:", AW
124   - assoc_mask_ORs = []
125   - pos_0s_AW = [x for x in range(len(AW)) if AW[x] == '0']
126   - rd.shuffle(pos_0s_AW)
127   - pos_1s_AW = [x for x in range(len(AW)) if AW[x] == '1']
128   - rd.shuffle(pos_1s_AW)
129   - pos_0s_formatted_AW = [x for x in range(len(formatted_AW)) if formatted_AW[x] == '0']
130   - rd.shuffle(pos_0s_formatted_AW)
131   - pos_1s_formatted_AW = [x for x in range(len(formatted_AW)) if formatted_AW[x] == '1']
132   - rd.shuffle(pos_1s_formatted_AW)
133   - vhd_file.write(" -- Formatted AW: "+formatted_AW[::-1]+", MSB first\n")
134   - vhd_file.write(" -- AW: "+AW[::-1]+", MSB first\n")
135   - if masking and not locking:
136   - fan_in_ANDs = float(len([x for x in formatted_AW if x == '1']))/(len([x for x in AW if x == '1']))
137   - fan_in_ORs = float(len([x for x in formatted_AW if x == '0']))/(len([x for x in AW if x == '0']))
138   - assoc_mask_ANDs = gen_assoc_mask_ANDs (fan_in_ANDs, pos_1s_AW, pos_1s_formatted_AW)
139   - assoc_mask_ORs = gen_assoc_mask_ORs (fan_in_ORs, pos_0s_AW, pos_0s_formatted_AW)
140   - print "Mask ANDs", assoc_mask_ANDs
141   - print "Mask ORs", assoc_mask_ORs
142   - vhd_file.write("\n -- Mask ANDs\n")
143   - for (inputs, outputs) in assoc_mask_ANDs:
144   - if type(inputs) == int and type(outputs) == int:
145   - vhd_file.write(" AW("+str(outputs)+") <= formatted_AW("+str(inputs)+");\n")
146   - elif type(inputs) == int and type(outputs) == list:
147   - for output in outputs:
148   - vhd_file.write(" AW("+str(output)+") <= formatted_AW("+str(inputs)+")\n")
149   - elif type(inputs) == list and type(outputs) == int:
150   - vhd_file.write(" AW("+str(outputs)+") <= "+" AND ".join(["formatted_AW("+str(i)+")" for i in inputs])+";\n")
151   - vhd_file.write("\n -- Mask ORs\n")
152   - for (inputs, outputs) in assoc_mask_ORs:
153   - if type(inputs) == int and type(outputs) == int:
154   - vhd_file.write(" AW("+str(outputs)+") <= formatted_AW("+str(inputs)+");\n")
155   - elif type(inputs) == int and type(outputs) == list:
156   - for output in outputs:
157   - vhd_file.write(" AW("+str(output)+") <= formatted_AW("+str(inputs)+");\n")
158   - elif type(inputs) == list and type(outputs) == int:
159   - vhd_file.write(" AW("+str(outputs)+") <= "+" OR ".join(["formatted_AW("+str(i)+")" for i in inputs])+";\n")
160   - if locking and not masking:
161   - assoc_lock_ANDs = [(pos_1s_formatted_AW, pos_1s_AW)]
162   - assoc_lock_ORs = [(pos_0s_formatted_AW, pos_0s_AW)]
163   - # for (inputs, outputs) in
164   - print "Lock ANDs", assoc_lock_ANDs
165   - print "Lock ORs", assoc_lock_ORs
166   - vhd_file.write("\n -- Lock AND\n")
167   - for (inputs, outputs) in assoc_lock_ANDs:
168   - vhd_file.write(" locking_1 <= "+" AND ".join(["formatted_AW("+str(i)+")" for i in inputs])+";\n")
169   - for output in outputs:
170   - vhd_file.write(" AW("+str(output)+") <= locking_1;\n")
171   - vhd_file.write("\n -- Lock OR\n")
172   - for (inputs, outputs) in assoc_lock_ORs:
173   - vhd_file.write(" locking_0 <= "+" OR ".join(["formatted_AW("+str(i)+")" for i in inputs])+";\n")
174   - for output in outputs:
175   - vhd_file.write(" AW("+str(output)+") <= locking_0;\n")
  156 +
  157 + if (masking and not locking) or (locking and not masking):
  158 + write_header(vhd_file, locking, width_formatted_AW, len(AW))
  159 + if not formatted_AW:
  160 + formatted_AW = ''.join([str(int(2*rd.random())) for i in xrange(width_formatted_AW)])
  161 + elif len(formatted_AW) != width_formatted_AW:
  162 + raise ValueError("Length of provided formatted AW does not match width_formatted_AW")
  163 + print "Formatted AW:", formatted_AW
  164 + print " AW:", AW
  165 + print unlocking_word
  166 + print unmasking_word
  167 + vhd_file.write(" -- Formatted AW: "+formatted_AW+"\n")
  168 + vhd_file.write(" -- AW: "+AW+"\n")
  169 +
  170 + pos_0s_AW = [len(AW)-1-x for x in range(len(AW)) if AW[x] == '0']
  171 + rd.shuffle(pos_0s_AW)
  172 + pos_1s_AW = [len(AW)-1-x for x in range(len(AW)) if AW[x] == '1']
  173 + rd.shuffle(pos_1s_AW)
  174 + pos_0s_formatted_AW = [len(AW)-1-x for x in range(len(formatted_AW)) if formatted_AW[x] == '0']
  175 + rd.shuffle(pos_0s_formatted_AW)
  176 + pos_1s_formatted_AW = [len(AW)-1-x for x in range(len(formatted_AW)) if formatted_AW[x] == '1']
  177 + rd.shuffle(pos_1s_formatted_AW)
  178 + if locking and not masking:
  179 + assoc_lock_ANDs = [(pos_1s_formatted_AW, pos_1s_AW)]
  180 + assoc_lock_ORs = [(pos_0s_formatted_AW, pos_0s_AW)]
  181 + # for (inputs, outputs) in
  182 + write_locking_part_to_file(vhd_file, assoc_lock_ANDs, assoc_lock_ORs)
  183 + if masking and not locking:
  184 + fan_in_ANDs = float(len([x for x in formatted_AW if x == '1']))/(len([x for x in AW if x == '1']))
  185 + fan_in_ORs = float(len([x for x in formatted_AW if x == '0']))/(len([x for x in AW if x == '0']))
  186 + assoc_mask_ANDs = gen_assoc_mask_ANDs (fan_in_ANDs, pos_1s_AW, pos_1s_formatted_AW)
  187 + assoc_mask_ORs = gen_assoc_mask_ORs (fan_in_ORs, pos_0s_AW, pos_0s_formatted_AW)
  188 + write_masking_part_to_file(vhd_file, assoc_mask_ANDs, assoc_mask_ORs)
  189 + if masking and locking:
  190 + write_header(vhd_file, locking, width_formatted_AW, len(AW)-1)
  191 + formatted_AW_locking = ""
  192 + formatted_AW_masking = ""
  193 + if not formatted_AW:
  194 + while set(formatted_AW_locking) != set(['0', '1']):
  195 + formatted_AW_locking = ''.join([str(int(2*rd.random())) for i in xrange(width_formatted_AW/2)])
  196 + while set(formatted_AW_masking) != set(['0', '1']):
  197 + formatted_AW_masking = ''.join([str(int(2*rd.random())) for i in xrange(width_formatted_AW/2)])
  198 + elif len(formatted_AW) != width_formatted_AW:
  199 + raise ValueError("Length of provided formatted AW does not match width_formatted_AW")
  200 + else:
  201 + formatted_AW_locking = formatted_AW[len(formatted_AW)/2:]
  202 + formatted_AW_masking = formatted_AW[:len(formatted_AW)/2]
  203 + print "Formatted AW:", formatted_AW_locking+formatted_AW_masking
  204 + print " AW:", AW
  205 + print "Formatted AW locking", formatted_AW_locking
  206 + print "Formatted AW masking", formatted_AW_masking
  207 + vhd_file.write(" -- Formatted AW: "+formatted_AW_locking+formatted_AW_masking+"\n")
  208 + vhd_file.write(" -- AW: "+AW+"\n")
  209 +
  210 + pos_0s_unlocking_word = [len(AW)-2-x for x in range(len(unlocking_word)) if unlocking_word[x] == '0']
  211 + rd.shuffle(pos_0s_unlocking_word)
  212 + pos_1s_unlocking_word = [len(AW)-2-x for x in range(len(unlocking_word)) if unlocking_word[x] == '1']
  213 + rd.shuffle(pos_1s_unlocking_word)
  214 + pos_0s_unmasking_word = [len(AW)-len(unlocking_word)-2-x for x in range(len(unmasking_word)) if unmasking_word[x] == '0']
  215 + rd.shuffle(pos_0s_unmasking_word)
  216 + pos_1s_unmasking_word = [len(AW)-len(unlocking_word)-2-x for x in range(len(unmasking_word)) if unmasking_word[x] == '1']
  217 + rd.shuffle(pos_1s_unmasking_word)
  218 + pos_0s_formatted_AW_locking = [len(formatted_AW_locking)+len(formatted_AW_masking)-1-x for x in range(len(formatted_AW_locking)) if formatted_AW_locking[x] == '0']
  219 + rd.shuffle(pos_0s_formatted_AW_locking)
  220 + pos_1s_formatted_AW_locking = [len(formatted_AW_locking)+len(formatted_AW_masking)-1-x for x in range(len(formatted_AW_locking)) if formatted_AW_locking[x] == '1']
  221 + rd.shuffle(pos_1s_formatted_AW_locking)
  222 + pos_0s_formatted_AW_masking = [len(formatted_AW_masking)-1-x for x in range(len(formatted_AW_masking)) if formatted_AW_masking[x] == '0']
  223 + rd.shuffle(pos_0s_formatted_AW_masking)
  224 + pos_1s_formatted_AW_masking = [len(formatted_AW_masking)-1-x for x in range(len(formatted_AW_masking)) if formatted_AW_masking[x] == '1']
  225 + rd.shuffle(pos_1s_formatted_AW_masking)
  226 +
  227 + # Locking
  228 + assoc_lock_ANDs = [(pos_1s_formatted_AW_locking, pos_1s_unlocking_word)]
  229 + assoc_lock_ORs = [(pos_0s_formatted_AW_locking, pos_0s_unlocking_word)]
  230 + write_locking_part_to_file(vhd_file, assoc_lock_ANDs, assoc_lock_ORs)
  231 +
  232 + # Masking
  233 + fan_in_ANDs = float(len([x for x in formatted_AW_masking if x == '1']))/(len([x for x in unmasking_word if x == '1']))
  234 + fan_in_ORs = float(len([x for x in formatted_AW_masking if x == '0']))/(len([x for x in unmasking_word if x == '0']))
  235 + assoc_mask_ANDs = gen_assoc_mask_ANDs (fan_in_ANDs, pos_1s_unmasking_word, pos_1s_formatted_AW_masking)
  236 + assoc_mask_ORs = gen_assoc_mask_ORs (fan_in_ORs, pos_0s_unmasking_word, pos_0s_formatted_AW_masking)
  237 + write_masking_part_to_file(vhd_file, assoc_mask_ANDs, assoc_mask_ORs)
  238 +
176 239 vhd_file.write("\nEND ARCHITECTURE rtl;\n")
177 240  
178 241 return formatted_AW
179 242  
180 243 if __name__ == "__main__":
181   - # gen_AW_decoder("00000011", 8, locking=False, masking=True) # AW given LSB first
  244 + # gen_AW_decoder("00000011", 8, locking=False, masking=True)
182 245 # gen_AW_decoder("01010101", 8, locking=True, masking=False)
183   - gen_AW_decoder("0101 0101", 8, locking=True, masking=True)
184   -
  246 + gen_AW_decoder("11111110 10011000", 8, locking=True, masking=True)