Commit 6d251a84f6e951207a38c5e935afc0482afe08ce

Authored by Brice Colombier
1 parent 71a3d61544
Exists in master

refactor modules in app.py

Showing 2 changed files with 38 additions and 37 deletions

add_frame_elements.py View file @ 6d251a8
... ... @@ -198,14 +198,14 @@
198 198 column=0,
199 199 sticky=E)
200 200 self.generated_design_format_bench = Radiobutton(self.generate_modified_design_frame,
201   - text=".txt",
  201 + text="BENCH (.txt)",
202 202 variable=self.generated_design_format,
203 203 value="bench")
204 204 self.generated_design_format_bench.grid(row=0,
205 205 column=1,
206 206 sticky=W)
207 207 self.generated_design_format_vhd = Radiobutton(self.generate_modified_design_frame,
208   - text=".vhd",
  208 + text="VHDL (.vhd)",
209 209 variable=self.generated_design_format,
210 210 value="vhd")
211 211 self.generated_design_format_vhd.grid(row=1,
... ... @@ -24,11 +24,11 @@
24 24 import status_bar
25 25  
26 26  
27   -from key_derivation import blake2
  27 +from key_derivation.blake2 import BLAKE2s
28 28  
29   -# import locking
  29 +from locking.locking import locking
30 30  
31   -# import masking
  31 +from masking.masking import masking
32 32  
33 33 from parsers.build_bench import build as build_bench
34 34 from parsers.build_blif import build as build_blif
... ... @@ -40,8 +40,8 @@
40 40 from parsers.build_vhd_struct import build as build_vhd_struct
41 41 from parsers.build_xilinx import build as build_xilinx
42 42  
43   -from generate_modified_netlist import convert_back_bench
44   -from generate_modified_netlist import convert_back_vhd
  43 +from generate_modified_netlist.convert_back_bench import convert_back as convert_back_bench
  44 +from generate_modified_netlist.convert_back_vhd import convert_back as convert_back_vhd
45 45  
46 46 from boards_management import board_commands
47 47  
48 48  
49 49  
50 50  
51 51  
52 52  
53 53  
54 54  
55 55  
... ... @@ -104,23 +104,23 @@
104 104 self.master.update()
105 105 try:
106 106 if self.design_format.get() == "BENCH":
107   - self.g, self.prim_in, self.prim_out, self.nodes = build_bench.build(self.filename.get())
  107 + self.g, self.prim_in, self.prim_out, self.nodes = build_bench(self.filename.get())
108 108 elif self.design_format.get() == "BLIF":
109   - self.g, self.prim_in, self.prim_out, self.nodes = build_blif.build(self.filename.get())
  109 + self.g, self.prim_in, self.prim_out, self.nodes = build_blif(self.filename.get())
110 110 elif self.design_format.get() == "SLIF":
111   - self.g, self.prim_in, self.prim_out, self.nodes = build_slif.build(self.filename.get())
  111 + self.g, self.prim_in, self.prim_out, self.nodes = build_slif(self.filename.get())
112 112 elif self.design_format.get() == "EDIF":
113   - self.g, self.prim_in, self.prim_out, self.nodes = build_edif.build(self.filename.get())
  113 + self.g, self.prim_in, self.prim_out, self.nodes = build_edif(self.filename.get())
114 114 elif self.design_format.get() == "Xilinx EDIF":
115   - self.g, self.prim_in, self.prim_out, self.nodes = build_xilinx.build(self.filename.get())
  115 + self.g, self.prim_in, self.prim_out, self.nodes = build_xilinx(self.filename.get())
116 116 elif self.design_format.get() == "VHDL Dataflow":
117   - self.g, self.prim_in, self.prim_out, self.nodes = build_vhd_rtl.build(self.filename.get())
  117 + self.g, self.prim_in, self.prim_out, self.nodes = build_vhd_rtl(self.filename.get())
118 118 elif self.design_format.get() == "VHDL Structural":
119   - self.g, self.prim_in, self.prim_out, self.nodes = build_vhd_struct.build(self.filename.get())
  119 + self.g, self.prim_in, self.prim_out, self.nodes = build_vhd_struct(self.filename.get())
120 120 elif self.design_format.get() == "Verilog Dataflow":
121   - self.g, self.prim_in, self.prim_out, self.nodes = build_verilog_rtl.build(self.filename.get())
  121 + self.g, self.prim_in, self.prim_out, self.nodes = build_verilog_rtl(self.filename.get())
122 122 elif self.design_format.get() == "Verilog Structural":
123   - self.g, self.prim_in, self.prim_out, self.nodes = build_verilog_struct.build(self.filename.get())
  123 + self.g, self.prim_in, self.prim_out, self.nodes = build_verilog_struct(self.filename.get())
124 124 self.graph_info.set(str(str(len(self.nodes))+" nodes, "+
125 125 str(len(self.prim_in))+" inputs, "+
126 126 str(len(self.prim_out))+" outputs."))
127 127  
128 128  
129 129  
130 130  
... ... @@ -224,33 +224,33 @@
224 224 self.unlocking_word = ""
225 225 self.unmasking_word = ""
226 226 if self.locking.get():
227   - self.graph_modified, self.unlocking_word = locking.locking(self.g,
228   - self.prim_in,
229   - self.prim_out,
230   - self.nodes,
231   - self.locking_overhead.get())
  227 + self.graph_modified, self.unlocking_word = locking(self.g,
  228 + self.prim_in,
  229 + self.prim_out,
  230 + self.nodes,
  231 + self.locking_overhead.get())
232 232 if self.masking.get():
233   - self.graph_modified, self.unmasking_word = masking.masking(self.graph_modified,
234   - self.prim_in,
235   - self.prim_out,
236   - self.nodes,
237   - self.masking_overhead.get(),
238   - self.masking_heuristic.get())
  233 + self.graph_modified, self.unmasking_word = masking(self.graph_modified,
  234 + self.prim_in,
  235 + self.prim_out,
  236 + self.nodes,
  237 + self.masking_overhead.get(),
  238 + self.masking_heuristic.get())
239 239 elif self.masking.get():
240   - self.graph_modified, self.unmasking_word = masking.masking(self.g,
241   - self.prim_in,
242   - self.prim_out,
243   - self.nodes,
244   - self.masking_overhead.get(),
245   - self.masking_heuristic.get())
  240 + self.graph_modified, self.unmasking_word = masking(self.g,
  241 + self.prim_in,
  242 + self.prim_out,
  243 + self.nodes,
  244 + self.masking_overhead.get(),
  245 + self.masking_heuristic.get())
246 246 print self.unlocking_word, self.unmasking_word
247 247  
248 248 def derive_key_from_response(self):
249 249 self.salt = bytes(''.join(random.SystemRandom().choice(["0", "1"]) for _ in range(32)))
250   - PRK_f = blake2.BLAKE2s(digest_size=32, key=self.salt)
  250 + PRK_f = BLAKE2s(digest_size=32, key=self.salt)
251 251 PRK_f.update(self.PUF_reference_response)
252 252 self.key = ''.join('{0:08b}'.format(ord(x), 'b') for x in PRK_f.final()).replace("0b", "")
253   - key_file_name = "./../User_space/key_"+""+".txt"
  253 + key_file_name = "./user_space/key_"+""+".txt"
254 254 with open(key_file_name, "w") as key_file:
255 255 key_file.write("Salt = "+self.salt+"\n")
256 256 key_file.write("Key = "+self.key)
257 257  
258 258  
... ... @@ -264,18 +264,19 @@
264 264 filename[1] = "vhd"
265 265 filename = ".".join(filename)
266 266 filename = "/".join(self.filename.get().split("/")[:-1])+"/"+filename
267   - convert_back_vhd.convert_back(self.graph_modified, filename)
  267 + convert_back_vhd(self.graph_modified, filename)
268 268 elif self.generated_design_format.get() == "bench":
269 269 filename[1] = "txt"
270 270 filename = ".".join(filename)
271 271 filename = "/".join(self.filename.get().split("/")[:-1])+"/"+filename
272   - convert_back_bench.convert_back(self.graph_modified, filename)
  272 + convert_back_bench(self.graph_modified, filename)
273 273 self.message_modified_design_saved.set(str("Modified design saved under "+filename))
274 274  
275 275 def save_AW(self):
276 276 filename = self.filename.get().split("/")[-1]
277 277 filename = filename.split(".")
278 278 filename[0]+="_mod_AW"
  279 + filename[1] = "txt"
279 280 filename = ".".join(filename)
280 281 filename = "/".join(self.filename.get().split("/")[:-1])+"/"+filename
281 282 with open(filename, "w") as aw_file: