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Commit 6a27f428b84e6f22a79fd819551c6221dfc899cb

Authored by Brice Colombier
1 parent 381180d950
Exists in master

Keyed renamed to activable

Showing 3 changed files with 131 additions and 131 deletions

activable_design/generate_activable_design.py View file @ 6a27f42
  1 +import re
  2 +
  3 +def get_entity(modified_design_file_name):
  4 +
  5 + with open(modified_design_file_name, "r") as design_file:
  6 + for line in design_file:
  7 + if "ENTITY" in line and "IS" in line:
  8 + entity_name = re.search('ENTITY [A-Za-z_0-9]* IS', line.upper()).group(0).replace("ENTITY", "").replace("IS", "").strip().lower().replace("_mod", "")
  9 + break
  10 + return entity_name
  11 +
  12 +
  13 +def write_entity(target_file,
  14 + modified_design_file_name,
  15 + entity_name,
  16 + locking_inputs,
  17 + masking_inputs):
  18 + target_file.write("LIBRARY ieee;\n")
  19 + target_file.write("USE ieee.std_logic_1164.ALL;\n")
  20 + target_file.write("\n")
  21 + target_file.write("ENTITY "+entity_name+"_activable IS\n")
  22 + target_file.write("\n")
  23 + target_file.write(" PORT (\n")
  24 + inputs = []
  25 + outputs = []
  26 + with open(modified_design_file_name, "r") as design_file:
  27 + for line in design_file:
  28 + if "IN STD_LOGIC" in line.upper():
  29 + input_name = line.split(":")[0].strip()
  30 + if input_name not in locking_inputs and input_name not in masking_inputs:
  31 + if "IN STD_LOGIC_VECTOR" in line.upper():
  32 + if "DOWNTO" in line:
  33 + vector_range = re.search('\([0-9]* DOWNTO [0-9]*\)', line.upper()).group(0)[1:-1].replace(" ", "").split("DOWNTO")
  34 + target_file.write(" "+input_name+" : IN STD_LOGIC_VECTOR("+vector_range[0]+" DOWNTO "+vector_range[1]+");\n")
  35 + elif "TO" in line:
  36 + vector_range = re.search('\([0-9]* TO [0-9]*\)', line.upper()).group(0)[1:-1].replace(" ", "").split("TO")
  37 + target_file.write(" "+input_name+" : IN STD_LOGIC_VECTOR("+vector_range[0]+" TO "+vector_range[1]+");\n")
  38 + else:
  39 + target_file.write(" "+line.split(":")[0].strip()+" : IN STD_LOGIC;\n")
  40 + inputs.append(line.split(":")[0].strip())
  41 + elif "OUT STD_LOGIC" in line.upper():
  42 + if "OUT STD_LOGIC_VECTOR" in line.upper():
  43 + if "DOWNTO" in line:
  44 + vector_range = re.search('\([0-9]* DOWNTO [0-9]*\)', line.upper()).group(0)[1:-1].replace(" ", "").split("DOWNTO")
  45 + target_file.write(" "+line.split(":")[0].strip()+" : OUT STD_LOGIC_VECTOR("+vector_range[0]+" DOWNTO "+vector_range[1]+");\n")
  46 + elif "TO" in line:
  47 + vector_range = re.search('\([0-9]* TO [0-9]*\)', line.upper()).group(0)[1:-1].replace(" ", "").split("TO")
  48 + target_file.write(" "+line.split(":")[0].strip()+" : OUT STD_LOGIC_VECTOR("+vector_range[0]+" TO "+vector_range[1]+");\n")
  49 + else:
  50 + target_file.write(" "+line.split(":")[0].strip()+" : OUT STD_LOGIC;\n")
  51 + outputs.append(line.split(":")[0].strip())
  52 + target_file.write(" key : IN STD_LOGIC_VECTOR(127 DOWNTO 0)\n );\n\n")
  53 + target_file.write("END ENTITY "+entity_name+"_activable;\n\n")
  54 + return inputs, outputs
  55 +
  56 +def write_architecture(target_file,
  57 + entity_name,
  58 + locking,
  59 + masking,
  60 + inputs,
  61 + outputs):
  62 + target_file.write("ARCHITECTURE rtl OF "+entity_name+"_activable IS\n\n")
  63 + if locking[0] and masking[0]:
  64 + target_file.write(" SIGNAL AW_locking : STD_LOGIC_VECTOR("+str(len(locking[1])-1)+" DOWNTO 0);\n")
  65 + target_file.write(" SIGNAL AW_masking : STD_LOGIC_VECTOR(0 TO "+str(len(masking[1])-1)+");\n")
  66 + target_file.write(" SIGNAL AW : STD_LOGIC_VECTOR(0 TO "+str(len(masking[1])+len(locking[1])-1)+");\n\n")
  67 + if locking[0] and not masking[0]:
  68 + target_file.write(" SIGNAL AW : STD_LOGIC_VECTOR("+str(len(locking[1])-1)+" DOWNTO 0);\n\n")
  69 + if not locking[0] and masking[0]:
  70 + target_file.write(" SIGNAL AW : STD_LOGIC_VECTOR(0 TO "+str(len(masking[1])-1)+");\n\n")
  71 + target_file.write("BEGIN\n\n")
  72 + target_file.write(" AW_decoder_1: ENTITY work.AW_decoder\n")
  73 + target_file.write(" PORT MAP (\n")
  74 + target_file.write(" formatted_AW => key,\n")
  75 + target_file.write(" AW => AW);\n\n")
  76 + if locking[0] and masking[0]:
  77 + target_file.write(" AW_locking <= AW(0 TO "+str(len(locking[1])-1)+");\n")
  78 + target_file.write(" AW_masking <= AW("+str(len(locking[1]))+" TO "+str(len(locking[1])+len(masking[1])-1)+");\n\n")
  79 + target_file.write(" "+entity_name+"_mod_1: ENTITY work."+entity_name+"_mod\n")
  80 + target_file.write(" PORT MAP (\n")
  81 + for input_net in inputs:
  82 + target_file.write(" "+input_net+" => "+input_net+",\n")
  83 + if locking[0] and masking[0]:
  84 + for index, locking_input in enumerate(locking[1]):
  85 + target_file.write(" "+locking_input+" => AW_locking("+str(index)+"),\n")
  86 + for index, masking_input in enumerate(masking[1]):
  87 + target_file.write(" "+masking_input+" => AW_masking("+str(index)+"),\n")
  88 + elif locking[0] and not masking[0]:
  89 + for index, locking_input in enumerate(locking[1]):
  90 + target_file.write(" "+locking_input+" => AW("+str(index)+"),\n")
  91 + elif not locking[0] and masking[0]:
  92 + for index, masking_input in enumerate(masking[1]):
  93 + target_file.write(" "+masking_input+" => AW("+str(index)+"),\n")
  94 + for output in outputs:
  95 + if output == outputs[-1]:
  96 + target_file.write(" "+output+" => "+output+");\n\n")
  97 + else:
  98 + target_file.write(" "+output+" => "+output+",\n")
  99 + target_file.write("END ARCHITECTURE rtl;")
  100 +
  101 +
  102 +def generate_activable_design(modified_design_file_name,
  103 + AW_decoder_file_name,
  104 + locking,
  105 + masking):
  106 + target_file_name = modified_design_file_name.replace("mod", "activable")
  107 + print modified_design_file_name
  108 +
  109 + with open(target_file_name, "w") as target_file:
  110 + entity_name = get_entity(modified_design_file_name)
  111 + print entity_name
  112 + inputs, outputs = write_entity(target_file, modified_design_file_name, entity_name, locking[1], masking[1])
  113 + write_architecture(target_file, entity_name, locking, masking, inputs, outputs)
  114 +
  115 +if __name__ == "__main__":
  116 + locking_inputs = ["KG180gat", "KG285gat", "KG356gat", "KG416gat", "KG381gat"]
  117 + masking_inputs = ["KG309gat", "KG203gat", "KG319gat", "KG213gat", "KG296gat", "KG357gat", "KG360gat", "KG199gat"]
  118 + generate_activable_design("./../user_space/c432_mod.vhd",
  119 + "./../user_space/AW_decoder.vhd",
  120 + (True, locking_inputs),
  121 + (True, masking_inputs),
  122 + "./../user_space/c432_activable.vhd")
  123 +
app.py View file @ 6a27f42
... ... @@ -51,7 +51,7 @@
51 51  
52 52 from AW_decoder.gen_AW_decoder import gen_AW_decoder
53 53  
54   -from keyed_design.generate_keyed_design import generate_keyed_design
  54 +from activable_design.generate_activable_design import generate_activable_design
55 55  
56 56 class App:
57 57  
58 58  
... ... @@ -101,12 +101,9 @@
101 101 # Enrolment frame
102 102 self.setState(self.get_PUF_response_frame, state = "disabled")
103 103  
104   -
105   -
106 104 def select_file(self):
107 105 self.update_status("")
108 106  
109   -
110 107 ftypes = [("All netlist files", ".txt; .blif; .slif; .edf; .vhd; .v"),
111 108 ("BENCH files", ".txt"),
112 109 ("BLIF files", ".blif"),
... ... @@ -408,6 +405,8 @@
408 405 aw_file.write("Unlocking word concatenated with unmasking word\n"+self.unlocking_word+" "+self.unmasking_word)
409 406 self.update_status(str("Associated activation word saved under "+filename))
410 407 self.setState(self.wrap_modified_design_frame, state = "normal")
  408 + self.select_crypto_PRESENT.configure(state = "disabled")
  409 + self.select_key_derivation_blake2.configure(state = "disabled")
411 410 self.setState(self.generate_save_modified_design_frame, state = "disabled")
412 411  
413 412  
414 413  
415 414  
... ... @@ -456,14 +455,14 @@
456 455 except:
457 456 self.update_status("An error occured while generating the AW decoder")
458 457 try:
459   - generate_keyed_design("./user_space/"+self.filename.get().split("/")[-1].split(".")[0]+"_mod.vhd",
  458 + generate_activable_design("./user_space/"+self.filename.get().split("/")[-1].split(".")[0]+"_mod.vhd",
460 459 "./user_space/AW_decoder.vhd",
461 460 (locking, self.locking_inputs),
462 461 (masking, self.masking_inputs))
463   - self.update_status("Keyed design generated")
  462 + self.update_status("Activable design generated")
464 463 except Exception as e:
465 464 print e
466   - self.update_status("An error occured while generating the keyed design")
  465 + self.update_status("An error occured while generating the activable design")
467 466 self.master.config(cursor="")
468 467 self.master.update()
469 468  
... ... @@ -516,6 +515,8 @@
516 515 pass
517 516 for child in widget.winfo_children():
518 517 self.setState(child, state=state)
  518 +
  519 +
519 520  
520 521 if __name__ == "__main__":
521 522  
keyed_design/generate_keyed_design.py View file @ 6a27f42
1   -import re
2   -
3   -def get_entity(modified_design_file_name):
4   -
5   - with open(modified_design_file_name, "r") as design_file:
6   - for line in design_file:
7   - if "ENTITY" in line and "IS" in line:
8   - entity_name = re.search('ENTITY [A-Za-z_0-9]* IS', line.upper()).group(0).replace("ENTITY", "").replace("IS", "").strip().lower().replace("_mod", "")
9   - break
10   - return entity_name
11   -
12   -
13   -def write_entity(target_file,
14   - modified_design_file_name,
15   - entity_name,
16   - locking_inputs,
17   - masking_inputs):
18   - target_file.write("LIBRARY ieee;\n")
19   - target_file.write("USE ieee.std_logic_1164.ALL;\n")
20   - target_file.write("\n")
21   - target_file.write("ENTITY "+entity_name+"_activable IS\n")
22   - target_file.write("\n")
23   - target_file.write(" PORT (\n")
24   - inputs = []
25   - outputs = []
26   - with open(modified_design_file_name, "r") as design_file:
27   - for line in design_file:
28   - if "IN STD_LOGIC" in line.upper():
29   - input_name = line.split(":")[0].strip()
30   - if input_name not in locking_inputs and input_name not in masking_inputs:
31   - if "IN STD_LOGIC_VECTOR" in line.upper():
32   - if "DOWNTO" in line:
33   - vector_range = re.search('\([0-9]* DOWNTO [0-9]*\)', line.upper()).group(0)[1:-1].replace(" ", "").split("DOWNTO")
34   - target_file.write(" "+input_name+" : IN STD_LOGIC_VECTOR("+vector_range[0]+" DOWNTO "+vector_range[1]+");\n")
35   - elif "TO" in line:
36   - vector_range = re.search('\([0-9]* TO [0-9]*\)', line.upper()).group(0)[1:-1].replace(" ", "").split("TO")
37   - target_file.write(" "+input_name+" : IN STD_LOGIC_VECTOR("+vector_range[0]+" TO "+vector_range[1]+");\n")
38   - else:
39   - target_file.write(" "+line.split(":")[0].strip()+" : IN STD_LOGIC;\n")
40   - inputs.append(line.split(":")[0].strip())
41   - elif "OUT STD_LOGIC" in line.upper():
42   - if "OUT STD_LOGIC_VECTOR" in line.upper():
43   - if "DOWNTO" in line:
44   - vector_range = re.search('\([0-9]* DOWNTO [0-9]*\)', line.upper()).group(0)[1:-1].replace(" ", "").split("DOWNTO")
45   - target_file.write(" "+line.split(":")[0].strip()+" : OUT STD_LOGIC_VECTOR("+vector_range[0]+" DOWNTO "+vector_range[1]+");\n")
46   - elif "TO" in line:
47   - vector_range = re.search('\([0-9]* TO [0-9]*\)', line.upper()).group(0)[1:-1].replace(" ", "").split("TO")
48   - target_file.write(" "+line.split(":")[0].strip()+" : OUT STD_LOGIC_VECTOR("+vector_range[0]+" TO "+vector_range[1]+");\n")
49   - else:
50   - target_file.write(" "+line.split(":")[0].strip()+" : OUT STD_LOGIC;\n")
51   - outputs.append(line.split(":")[0].strip())
52   - target_file.write(" key : IN STD_LOGIC_VECTOR(127 DOWNTO 0)\n );\n\n")
53   - target_file.write("END ENTITY "+entity_name+"_activable;\n\n")
54   - return inputs, outputs
55   -
56   -def write_architecture(target_file,
57   - entity_name,
58   - locking,
59   - masking,
60   - inputs,
61   - outputs):
62   - target_file.write("ARCHITECTURE rtl OF "+entity_name+"_activable IS\n\n")
63   - if locking[0] and masking[0]:
64   - target_file.write(" SIGNAL AW_locking : STD_LOGIC_VECTOR("+str(len(locking[1])-1)+" DOWNTO 0);\n")
65   - target_file.write(" SIGNAL AW_masking : STD_LOGIC_VECTOR(0 TO "+str(len(masking[1])-1)+");\n")
66   - target_file.write(" SIGNAL AW : STD_LOGIC_VECTOR(0 TO "+str(len(masking[1])+len(locking[1])-1)+");\n\n")
67   - if locking[0] and not masking[0]:
68   - target_file.write(" SIGNAL AW : STD_LOGIC_VECTOR("+str(len(locking[1])-1)+" DOWNTO 0);\n\n")
69   - if not locking[0] and masking[0]:
70   - target_file.write(" SIGNAL AW : STD_LOGIC_VECTOR(0 TO "+str(len(masking[1])-1)+");\n\n")
71   - target_file.write("BEGIN\n\n")
72   - target_file.write(" AW_decoder_1: ENTITY work.AW_decoder\n")
73   - target_file.write(" PORT MAP (\n")
74   - target_file.write(" formatted_AW => key,\n")
75   - target_file.write(" AW => AW);\n\n")
76   - if locking[0] and masking[0]:
77   - target_file.write(" AW_locking <= AW(0 TO "+str(len(locking[1])-1)+");\n")
78   - target_file.write(" AW_masking <= AW("+str(len(locking[1]))+" TO "+str(len(locking[1])+len(masking[1])-1)+");\n\n")
79   - target_file.write(" "+entity_name+"_mod_1: ENTITY work."+entity_name+"_mod\n")
80   - target_file.write(" PORT MAP (\n")
81   - for input_net in inputs:
82   - target_file.write(" "+input_net+" => "+input_net+",\n")
83   - if locking[0] and masking[0]:
84   - for index, locking_input in enumerate(locking[1]):
85   - target_file.write(" "+locking_input+" => AW_locking("+str(index)+"),\n")
86   - for index, masking_input in enumerate(masking[1]):
87   - target_file.write(" "+masking_input+" => AW_masking("+str(index)+"),\n")
88   - elif locking[0] and not masking[0]:
89   - for index, locking_input in enumerate(locking[1]):
90   - target_file.write(" "+locking_input+" => AW("+str(index)+"),\n")
91   - elif not locking[0] and masking[0]:
92   - for index, masking_input in enumerate(masking[1]):
93   - target_file.write(" "+masking_input+" => AW("+str(index)+"),\n")
94   - for output in outputs:
95   - if output == outputs[-1]:
96   - target_file.write(" "+output+" => "+output+");\n\n")
97   - else:
98   - target_file.write(" "+output+" => "+output+",\n")
99   - target_file.write("END ARCHITECTURE rtl;")
100   -
101   -
102   -def generate_keyed_design(modified_design_file_name,
103   - AW_decoder_file_name,
104   - locking,
105   - masking):
106   - target_file_name = modified_design_file_name.replace("mod", "activable")
107   - print modified_design_file_name
108   -
109   - with open(target_file_name, "w") as target_file:
110   - entity_name = get_entity(modified_design_file_name)
111   - print entity_name
112   - inputs, outputs = write_entity(target_file, modified_design_file_name, entity_name, locking[1], masking[1])
113   - write_architecture(target_file, entity_name, locking, masking, inputs, outputs)
114   -
115   -if __name__ == "__main__":
116   - locking_inputs = ["KG180gat", "KG285gat", "KG356gat", "KG416gat", "KG381gat"]
117   - masking_inputs = ["KG309gat", "KG203gat", "KG319gat", "KG213gat", "KG296gat", "KG357gat", "KG360gat", "KG199gat"]
118   - generate_keyed_design("./../user_space/c432_mod.vhd",
119   - "./../user_space/AW_decoder.vhd",
120   - (True, locking_inputs),
121   - (True, masking_inputs),
122   - "./../user_space/c432_keyed.vhd")
123   -