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Commit 4751d2988d7febd4f9f5042c008aad9c1ba5aafc

Authored by Brice Colombier
1 parent 827f9062e6
Exists in master

Generate keyed design

Showing 1 changed file with 119 additions and 0 deletions

keyed_design/generate_keyed_design.py View file @ 4751d29
  1 +import re
  2 +
  3 +def get_entity(design_file_name):
  4 +
  5 + with open(design_file_name, "r") as design_file:
  6 + for line in design_file:
  7 + if "ENTITY" in line and "IS" in line:
  8 + entity_name = re.search('ENTITY [A-Za-z_]* IS', line.upper()).group(0).replace("ENTITY", "").replace("IS", "").strip().lower()
  9 + break
  10 + return entity_name
  11 +
  12 +
  13 +def write_entity(target_file,
  14 + design_file_name,
  15 + entity_name):
  16 + target_file.write("LIBRARY ieee;\n")
  17 + target_file.write("USE ieee.std_logic_1164.ALL;\n")
  18 + target_file.write("\n")
  19 + target_file.write("ENTITY keyed_"+entity_name+" IS\n")
  20 + target_file.write("\n")
  21 + target_file.write(" PORT (\n")
  22 + inputs = []
  23 + outputs = []
  24 + with open(design_file_name, "r") as design_file:
  25 + for line in design_file:
  26 + if "IN STD_LOGIC" in line.upper():
  27 + if "IN STD_LOGIC_VECTOR" in line.upper():
  28 + if "DOWNTO" in line:
  29 + vector_range = re.search('\([0-9]* DOWNTO [0-9]*\)', line.upper()).group(0)[1:-1].replace(" ", "").split("DOWNTO")
  30 + target_file.write(" "++line.split(":")[0].strip()+" : IN STD_LOGIC_VECTOR("+vector_range[0]+" DOWNTO "+vector_range[1]+");\n")
  31 + elif "TO" in line:
  32 + vector_range = re.search('\([0-9]* TO [0-9]*\)', line.upper()).group(0)[1:-1].replace(" ", "").split("TO")
  33 + target_file.write(" "++line.split(":")[0].strip()+" : IN STD_LOGIC_VECTOR("+vector_range[0]+" TO "+vector_range[1]+");\n")
  34 + else:
  35 + target_file.write(" "+line.split(":")[0].strip()+" : IN STD_LOGIC;\n")
  36 + inputs.append(line.split(":")[0].strip())
  37 + elif "OUT STD_LOGIC" in line.upper():
  38 + if "OUT STD_LOGIC_VECTOR" in line.upper():
  39 + if "DOWNTO" in line:
  40 + vector_range = re.search('\([0-9]* DOWNTO [0-9]*\)', line.upper()).group(0)[1:-1].replace(" ", "").split("DOWNTO")
  41 + target_file.write(" "++line.split(":")[0].strip()+" : OUT STD_LOGIC_VECTOR("+vector_range[0]+" DOWNTO "+vector_range[1]+");\n")
  42 + elif "TO" in line:
  43 + vector_range = re.search('\([0-9]* TO [0-9]*\)', line.upper()).group(0)[1:-1].replace(" ", "").split("TO")
  44 + target_file.write(" "++line.split(":")[0].strip()+" : OUT STD_LOGIC_VECTOR("+vector_range[0]+" TO "+vector_range[1]+");\n")
  45 + else:
  46 + target_file.write(" "+line.split(":")[0].strip()+" : OUT STD_LOGIC;\n")
  47 + outputs.append(line.split(":")[0].strip())
  48 + target_file.write(" key : IN STD_LOGIC_VECTOR(127 DOWNTO 0)\n );\n\n")
  49 + target_file.write("END ENTITY keyed_"+entity_name+";\n\n")
  50 + return inputs, outputs
  51 +
  52 +def write_architecture(target_file,
  53 + entity_name,
  54 + locking,
  55 + masking,
  56 + inputs,
  57 + outputs):
  58 + target_file.write("ARCHITECTURE rtl OF keyed_"+entity_name+" IS\n\n")
  59 + if locking[0] and masking[0]:
  60 + target_file.write(" SIGNAL AW_locking : STD_LOGIC_VECTOR("+str(len(locking[1])-1)+" DOWNTO 0);\n")
  61 + target_file.write(" SIGNAL AW_masking : STD_LOGIC_VECTOR(0 TO "+str(len(masking[1])-1)+");\n")
  62 + target_file.write(" SIGNAL AW : STD_LOGIC_VECTOR(0 TO "+str(len(masking[1])+len(locking[1])-1)+");\n\n")
  63 + if locking[0] and not masking[0]:
  64 + target_file.write(" SIGNAL AW : STD_LOGIC_VECTOR("+str(len(locking[1])-1)+" DOWNTO 0);\n\n")
  65 + if not locking[0] and masking[0]:
  66 + target_file.write(" SIGNAL AW : STD_LOGIC_VECTOR(0 TO "+str(len(masking[1])-1)+");\n\n")
  67 + target_file.write("BEGIN\n\n")
  68 + target_file.write(" AW_decoder_1: ENTITY work.AW_decoder\n")
  69 + target_file.write(" PORT MAP (\n")
  70 + target_file.write(" formatted_AW => key,\n")
  71 + target_file.write(" AW => AW);\n\n")
  72 + if locking[0] and masking[0]:
  73 + target_file.write(" AW_locking <= AW(0 TO "+str(len(locking[1])-1)+");\n")
  74 + target_file.write(" AW_masking <= AW("+str(len(locking[1]))+" TO "+str(len(locking[1])+len(masking[1])-1)+");\n\n")
  75 + target_file.write(" "+entity_name+"_mod_1: "+entity_name+"_mod\n")
  76 + target_file.write(" PORT MAP (\n")
  77 + for input_net in inputs:
  78 + target_file.write(" "+input_net+" => "+input_net+",\n")
  79 + if locking[0] and masking[0]:
  80 + for index, locking_input in enumerate(locking[1]):
  81 + target_file.write(" "+locking_input+" => AW_locking("+str(index)+"),\n")
  82 + for index, masking_input in enumerate(masking[1]):
  83 + target_file.write(" "+masking_input+" => AW_masking("+str(index)+"),\n")
  84 + elif locking[0] and not masking[0]:
  85 + for index, locking_input in enumerate(locking[1]):
  86 + target_file.write(" "+locking_input+" => AW("+str(index)+"),\n")
  87 + elif not locking[0] and masking[0]:
  88 + for index, masking_input in enumerate(masking[1]):
  89 + target_file.write(" "+masking_input+" => AW("+str(index)+"),\n")
  90 + for output in outputs:
  91 + if output == outputs[-1]:
  92 + target_file.write(" "+output+" => "+output+");\n\n")
  93 + else:
  94 + target_file.write(" "+output+" => "+output+",\n")
  95 + target_file.write("END ARCHITECTURE rtl;")
  96 +
  97 +
  98 +def generate_keyed_design(design_file_name,
  99 + AW_decoder_file_name,
  100 + locking,
  101 + masking,
  102 + target_file_name):
  103 +
  104 + with open(target_file_name, "w") as target_file:
  105 + entity_name = get_entity(design_file_name)
  106 + inputs, outputs = write_entity(target_file, design_file_name, entity_name)
  107 + print inputs
  108 + print outputs
  109 + write_architecture(target_file, entity_name, locking, masking, inputs, outputs)
  110 +
  111 +if __name__ == "__main__":
  112 + locking_inputs = ["KG180gat", "KG285gat", "KG356gat", "KG416gat", "KG381gat"]
  113 + masking_inputs = ["KG309gat", "KG203gat", "KG319gat", "KG213gat", "KG296gat", "KG357gat", "KG360gat", "KG199gat"]
  114 + generate_keyed_design("./../user_space/sin.vhd",
  115 + "./../user_space/AW_decoder.vhd",
  116 + (True, locking_inputs),
  117 + (True, masking_inputs),
  118 + "./../user_space/sin_keyed.vhd")
  119 +