wrapper.vhd 11.3 KB
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY top IS

PORT (
n_reset_in : IN STD_LOGIC; -- GPIO 2 : E22
MB_clk_in : IN STD_LOGIC; -- GPIO 1 : G22 clk 1MHz from MB
serial_in : IN STD_LOGIC; -- DATA 3 N : L20
vec_in_1 : IN STD_LOGIC_VECTOR(45 DOWNTO 0);
vec_in_2 : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
a : IN STD_LOGIC;
b : IN STD_LOGIC;
c : IN STD_LOGIC;
d : IN STD_LOGIC;
serial_out : OUT STD_LOGIC; -- DATA 3 P : L21
led_out : OUT STD_LOGIC -- LED : V19
vec_out_1 : OUT STD_LOGIC_VECTOR(45 DOWNTO 0);
vec_out_2 : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
e : OUT STD_LOGIC;
f : OUT STD_LOGIC;
g : OUT STD_LOGIC;
h : OUT STD_LOGIC
);

END ENTITY top;

ARCHITECTURE rtl OF top IS

COMPONENT in_buf IS
PORT(
PAD_IN : IN STD_LOGIC_VECTOR(0 TO 0);
Y : OUT STD_LOGIC_VECTOR(0 TO 0)
);
END COMPONENT in_buf;

COMPONENT out_buf IS
PORT(
D : IN STD_LOGIC_VECTOR(0 TO 0);
PAD_OUT : OUT STD_LOGIC_VECTOR(0 TO 0)
);
END COMPONENT out_buf;

COMPONENT clk_buf IS
PORT(
CLK0 : IN STD_LOGIC;
GL0 : OUT STD_LOGIC;
LOCK : OUT STD_LOGIC
);
END COMPONENT clk_buf;

COMPONENT ssi IS
GENERIC (
WIDTH : INTEGER := 8 -- Data bus width (MAX=511)
);
PORT (
reset : IN STD_LOGIC; -- Positive reset
clk : IN STD_LOGIC; -- Input clock
data_in : IN STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0); -- Parallel data input (to be TX-ed)
load : IN STD_LOGIC; -- Input data load (TX start)
rx : IN STD_LOGIC; -- RX serial line
data_out : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0); -- Parallel data output (RX-ed data)
ready : OUT STD_LOGIC; -- RX data ready
tx_empty : OUT STD_LOGIC; -- TX buffer empty (ready to TX)
tx : OUT STD_LOGIC -- TX serial line
);
END COMPONENT ssi;

COMPONENT TEROPUF_core IS
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
ena : IN STD_LOGIC;
selec_in : IN STD_LOGIC_VECTOR(SEL_WIDTH-1 DOWNTO 0);
output_puf : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
strobe : OUT STD_LOGIC);
END COMPONENT TEROPUF_core;

COMPONENT controller IS
PORT (
clk : IN STD_LOGIC;
rst_n : IN STD_LOGIC;
data_received_ssi : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
data_received_ready : IN STD_LOGIC;
ssi_ready_to_transmit : IN STD_LOGIC;
PUF_data_ready : IN STD_LOGIC;
rst_PUF : OUT STD_LOGIC;
ena_PUF : OUT STD_LOGIC;
TERO_index : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
ena_response_shift_register : OUT STD_LOGIC;
select_data_ssi : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
send_data_SSI : OUT STD_LOGIC;
selected_PUF_bit_for_parity : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
ena_parity_computation : OUT STD_LOGIC;
rst_n_sync_parity_module : OUT STD_LOGIC;
ena_parity_shift_register : OUT STD_LOGIC;
rst_parity_register : OUT STD_LOGIC);
END COMPONENT controller;

COMPONENT shift_register_2_bits IS
GENERIC (
width : INTEGER);
PORT (
clk : IN STD_LOGIC;
rst_n : IN STD_LOGIC;
data_in : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
ena : IN STD_LOGIC;
data_out : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0));
END COMPONENT shift_register_2_bits;

COMPONENT mux4x64 IS
PORT (
data_in_0 : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
data_in_1 : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
data_in_2 : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
data_in_3 : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
selection : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
data_out : OUT STD_LOGIC_VECTOR(63 DOWNTO 0));
END COMPONENT mux4x64;

COMPONENT mux_tero IS
GENERIC (
WIDTH : INTEGER;
SELECT_WIDTH : INTEGER);
PORT (
data_in : IN STD_LOGIC_VECTOR(WIDTH - 1 DOWNTO 0);
selection : IN STD_LOGIC_VECTOR(SELECT_WIDTH - 1 DOWNTO 0);
data_out : OUT STD_LOGIC);
END COMPONENT mux_tero;

COMPONENT parity IS
PORT (
clk : IN STD_LOGIC;
rst_n : IN STD_LOGIC;
rst_n_sync : IN STD_LOGIC;
data : IN STD_LOGIC;
ena : IN STD_LOGIC;
par : OUT STD_LOGIC);
END COMPONENT parity;

COMPONENT shift_register IS
GENERIC (
width : INTEGER);
PORT (
clk : IN STD_LOGIC;
rst_n : IN STD_LOGIC;
data_in : IN STD_LOGIC;
ena : IN STD_LOGIC;
data_out : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0));
END COMPONENT shift_register;
COMPONENT test IS
PORT (
vec_in_1 : IN STD_LOGIC_VECTOR(45 DOWNTO 0);
vec_in_2 : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
a : IN STD_LOGIC;
b : IN STD_LOGIC;
c : IN STD_LOGIC;
d : IN STD_LOGIC;
vec_out_1 : OUT STD_LOGIC_VECTOR(45 DOWNTO 0);
vec_out_2 : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
e : OUT STD_LOGIC;
f : OUT STD_LOGIC;
g : OUT STD_LOGIC;
h : OUT STD_LOGIC
);
END COMPONENT test;

----------------------------------------
-- Interface signals from and to buffers
----------------------------------------
SIGNAL n_reset : STD_LOGIC;
SIGNAL tx : STD_LOGIC;
SIGNAL rx : STD_LOGIC;
SIGNAL MB_clk_s : STD_LOGIC;
SIGNAL ssi_clk : STD_LOGIC;
SIGNAL led_out_s : STD_LOGIC;

-------------------------------
-- internal signals declaration
-------------------------------

SIGNAL reset : STD_LOGIC;
SIGNAL ssi_data_to_transmit : STD_LOGIC_VECTOR(63 DOWNTO 0);
SIGNAL ssi_start_transmit : STD_LOGIC;
SIGNAL ssi_data_received : STD_LOGIC_VECTOR(63 DOWNTO 0);
SIGNAL ssi_data_received_ready : STD_LOGIC;
SIGNAL ssi_ready_to_transmit : STD_LOGIC;
SIGNAL ena_PUF : STD_LOGIC;
SIGNAL TERO_index : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL output_PUF : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL PUF_data_ready : STD_LOGIC;
SIGNAL rst_PUF : STD_LOGIC;
SIGNAL ena_response_shift_register : STD_LOGIC;
SIGNAL select_data_ssi : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL PUF_response : STD_LOGIC_VECTOR(127 DOWNTO 0);
SIGNAL PUF_response_bit : STD_LOGIC;
SIGNAL PUF_response_bit_index : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL ena_parity_computation : STD_LOGIC;
SIGNAL ena_parity_shift_register : STD_LOGIC;
SIGNAL parity_value : STD_LOGIC;
SIGNAL rst_parity_register : STD_LOGIC;
SIGNAL parity_register_value : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL rst_n_sync_parity : STD_LOGIC;

----------
-- Buffers
----------

n_reset_in_buffer : in_buf
PORT MAP (
PAD_IN(0) => n_reset_in,
Y(0) => n_reset
);

serial_in_buffer : in_buf
PORT MAP (
PAD_IN(0) => serial_in,
Y(0) => rx
);

MB_clk_in_buffer : in_buf
PORT MAP (
PAD_IN(0) => MB_clk_in,
Y(0) => MB_clk_s
);

ssi_clk_buf : clk_buf
PORT MAP (
CLK0 => MB_clk_s,
GL0 => ssi_clk,
LOCK => OPEN
);

serial_out_buf : out_buf
PORT MAP (
D(0) => tx,
PAD_OUT(0) => serial_out
);

led_out_buf : out_buf
PORT MAP (
D(0) => led_out_s,
PAD_OUT(0) => led_out
);

---------------------------
-- Components instantiation
---------------------------

ssi_inst : ssi
GENERIC MAP (
WIDTH => 64 -- Data bus width (MAX=511)
)
PORT MAP (
reset => reset, -- Positive reset
clk => ssi_clk, -- Input clock
data_in => ssi_data_to_transmit, -- Parallel data input (to be TX-ed)
load => ssi_start_transmit, -- Input data load (TX start)
rx => rx, -- RX serial line
data_out => ssi_data_received, -- Parallel data output (RX-ed data)
ready => ssi_data_received_ready, -- RX data ready
tx_empty => ssi_ready_to_transmit, -- TX buffer empty (ready to TX)
tx => tx -- TX serial line
);

TEROPUF : TEROPUF_core
PORT MAP (
clk => ssi_clk,
rst => rst_PUF,
ena => ena_PUF,
selec_in => TERO_index,
output_puf => output_puf,
strobe => PUF_data_ready);

controller_1 : controller
PORT MAP (
clk => ssi_clk,
rst_n => n_reset,
data_received_ssi => ssi_data_received,
data_received_ready => ssi_data_received_ready,
ssi_ready_to_transmit => ssi_ready_to_transmit,
PUF_data_ready => PUF_data_ready,
rst_PUF => rst_PUF,
ena_PUF => ena_PUF,
TERO_index => TERO_index,
ena_response_shift_register => ena_response_shift_register,
select_data_ssi => select_data_ssi,
send_data_ssi => ssi_start_transmit,
selected_PUF_bit_for_parity => PUF_response_bit_index,
ena_parity_computation => ena_parity_computation,
rst_n_sync_parity_module => rst_n_sync_parity,
ena_parity_shift_register => ena_parity_shift_register,
rst_parity_register => rst_parity_register);

response_shift_register : shift_register_2_bits
GENERIC MAP (
width => 128)
PORT MAP (
clk => ssi_clk,
rst_n => n_reset,
data_in => output_PUF,
ena => ena_response_shift_register,
data_out => PUF_response);

mux_data_to_ssi : mux4x64
PORT MAP (
data_in_0 => PUF_response(63 DOWNTO 0),
data_in_1 => PUF_response(127 DOWNTO 64),
data_in_2 => x"FFFFFFFF" & parity_register_value,
data_in_3 => x"0000000000000000",
selection => select_data_ssi,
data_out => ssi_data_to_transmit);

mux_response_bits_to_parity : mux_tero
GENERIC MAP (
WIDTH => 128,
SELECT_WIDTH => 7)
PORT MAP (
data_in => PUF_response,
selection => PUF_response_bit_index,
data_out => PUF_response_bit);

parity_computation_module : parity
PORT MAP (
clk => ssi_clk,
rst_n => n_reset,
rst_n_sync => rst_n_sync_parity,
data => PUF_response_bit,
ena => ena_parity_computation,
par => parity_value);

parity_shift_register : shift_register
GENERIC MAP (
width => 32)
PORT MAP (
clk => ssi_clk,
rst_n => rst_parity_register,
data_in => parity_value,
ena => ena_parity_shift_register,
data_out => parity_register_value);

test_1 : test
PORT MAP (
a => a,
b => b,
c => c,
d => d,
vec_in_1 => vec_in_1,
vec_in_2 => vec_in_2,
vec_out_1 => vec_out_1,
vec_out_2 => vec_out_2,
e => e,
f => f,
g => g,
h => h);

led_out_s <= ssi_start_transmit;
reset <= (NOT n_reset);

END ARCHITECTURE rtl;