----------------------------------------
  -- Interface signals from and to buffers 
  ----------------------------------------
  SIGNAL n_reset   : STD_LOGIC;
  SIGNAL tx        : STD_LOGIC;
  SIGNAL rx        : STD_LOGIC;
  SIGNAL MB_clk_s  : STD_LOGIC;
  SIGNAL ssi_clk   : STD_LOGIC;
  SIGNAL led_out_s : STD_LOGIC;

  -------------------------------
  -- internal signals declaration
  -------------------------------

  SIGNAL reset                       : STD_LOGIC;
  SIGNAL ssi_data_to_transmit        : STD_LOGIC_VECTOR(63 DOWNTO 0);
  SIGNAL ssi_start_transmit          : STD_LOGIC;
  SIGNAL ssi_data_received           : STD_LOGIC_VECTOR(63 DOWNTO 0);
  SIGNAL ssi_data_received_ready     : STD_LOGIC;
  SIGNAL ssi_ready_to_transmit       : STD_LOGIC;
  SIGNAL ena_PUF                     : STD_LOGIC;
  SIGNAL TERO_index                  : STD_LOGIC_VECTOR(6 DOWNTO 0);
  SIGNAL output_PUF                  : STD_LOGIC_VECTOR(1 DOWNTO 0);
  SIGNAL PUF_data_ready              : STD_LOGIC;
  SIGNAL rst_PUF                     : STD_LOGIC;
  SIGNAL ena_response_shift_register : STD_LOGIC;
  SIGNAL select_data_ssi             : STD_LOGIC_VECTOR(1 DOWNTO 0);
  SIGNAL PUF_response                : STD_LOGIC_VECTOR(127 DOWNTO 0);
  SIGNAL PUF_response_bit            : STD_LOGIC;
  SIGNAL PUF_response_bit_index      : STD_LOGIC_VECTOR(6 DOWNTO 0);
  SIGNAL ena_parity_computation      : STD_LOGIC;
  SIGNAL ena_parity_shift_register   : STD_LOGIC;
  SIGNAL parity_value                : STD_LOGIC;
  SIGNAL rst_parity_register         : STD_LOGIC;
  SIGNAL parity_register_value       : STD_LOGIC_VECTOR(31 DOWNTO 0);
  SIGNAL rst_n_sync_parity           : STD_LOGIC;