generate_wrapper.py 9.71 KB
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import re
import hashlib
import os

def identify_interface_signals(design_to_wrap):
"""Identify inputs and outputs of a VHDL design"""

inputs = []
outputs = []
input_vectors = []
output_vectors = []

with open(design_to_wrap, "r") as design_to_wrap_file:
for line in design_to_wrap_file:
if "STD_LOGIC" in line.upper():
if "VECTOR" in line.upper():
vector_range = re.search('\([0-9]* DOWNTO [0-9]*\)', line.upper()).group(0)[1:-1].replace(" ", "").split("DOWNTO")
if "IN" in line.upper():
input_vectors.append([line.split(":")[0], vector_range])
elif "OUT" in line.upper():
output_vectors.append([line.split(":")[0], vector_range])
else:
if "IN" in line.upper():
if "," in line.split(":")[0]:
inputs.extend(line.split(":")[0].split(","))
else:
inputs.append(line.split(":")[0])
elif "OUT" in line.upper():
if "," in line.split(":")[0]:
outputs.extend(line.split(":")[0].split(","))
else:
outputs.append(line.split(":")[0])
inputs = [i.strip() for i in inputs]
outputs = [i.strip() for i in outputs]
input_vectors = [[i[0].strip(), i[1]] for i in input_vectors]
output_vectors = [[i[0].strip(), i[1]] for i in output_vectors]
return inputs, outputs, input_vectors, output_vectors

def write_header(target_file_name):
with open(target_file_name, "w") as target_file:
target_file.write("LIBRARY ieee;\nUSE ieee.std_logic_1164.ALL;\n\n")

def write_entity(entity_name, target_file_name, inputs, outputs, input_vectors, output_vectors):
with open(target_file_name, "a") as target_file:
target_file.write("ENTITY "+entity_name+" IS\n\n PORT (\n")
target_file.write(" n_reset_in : IN STD_LOGIC; -- GPIO 2 : E22\n")
target_file.write(" MB_clk_in : IN STD_LOGIC; -- GPIO 1 : G22 clk 1MHz from MB\n")
target_file.write(" serial_in : IN STD_LOGIC; -- DATA 3 N : L20\n")
for i in input_vectors:
if i[1][0] > i[1][1]:
target_file.write(" "+i[0]+" : IN STD_LOGIC_VECTOR("+i[1][0]+" DOWNTO "+i[1][1]+");\n")
elif i[1][0] < i[1][1]:
target_file.write(" "+i[0]+" : IN STD_LOGIC_VECTOR("+i[1][0]+" TO "+i[1][1]+");\n")
else:
raise ValueError("Wrong STD_LOGIC_VECTOR range")
for i in inputs:
target_file.write(" "+i+" : IN STD_LOGIC;\n")
target_file.write(" serial_out : OUT STD_LOGIC; -- DATA 3 P : L21\n")
target_file.write(" led_out : OUT STD_LOGIC -- LED : V19 \n")
for i in output_vectors:
if i[1][0] > i[1][1]:
target_file.write(" "+i[0]+" : OUT STD_LOGIC_VECTOR("+i[1][0]+" DOWNTO "+i[1][1]+");\n")
elif i[1][0] < i[1][1]:
target_file.write(" "+i[0]+" : OUT STD_LOGIC_VECTOR("+i[1][0]+" TO "+i[1][1]+");\n")
else:
raise ValueError("Wrong STD_LOGIC_VECTOR range")
for i in outputs:
if i == outputs[-1]:
target_file.write(" "+i+" : OUT STD_LOGIC\n")
else:
target_file.write(" "+i+" : OUT STD_LOGIC;\n")
target_file.write(" );\n\n")
target_file.write("END ENTITY "+entity_name+";\n\n")

def write_architecture_components(design_to_wrap, entity_name, target_file_name, architecture_components_file_name, inputs, outputs, input_vectors, output_vectors):
with open(target_file_name, "a") as target_file:
target_file.write("ARCHITECTURE rtl OF "+entity_name+" IS\n")
with open(architecture_components_file_name, "r") as architecture_components_file:
for line in architecture_components_file:
target_file.write(line)
target_file.write(" COMPONENT "+design_to_wrap.split(".")[0]+" IS\n")
target_file.write(" PORT (\n")
for i in input_vectors:
if i[1][0] > i[1][1]:
target_file.write(" "+i[0]+" : IN STD_LOGIC_VECTOR("+i[1][0]+" DOWNTO "+i[1][1]+");\n")
elif i[1][0] < i[1][1]:
target_file.write(" "+i[0]+" : IN STD_LOGIC_VECTOR("+i[1][0]+" TO "+i[1][1]+");\n")
else:
raise ValueError("Wrong STD_LOGIC_VECTOR range")
for i in inputs:
target_file.write(" "+i+" : IN STD_LOGIC;\n")
for i in output_vectors:
if outputs:
if i[1][0] > i[1][1]:
target_file.write(" "+i[0]+" : OUT STD_LOGIC_VECTOR("+i[1][0]+" DOWNTO "+i[1][1]+");\n")
elif i[1][0] < i[1][1]:
target_file.write(" "+i[0]+" : OUT STD_LOGIC_VECTOR("+i[1][0]+" TO "+i[1][1]+");\n")
else:
raise ValueError("Wrong STD_LOGIC_VECTOR range")
else:
if i != output_vectors[-1]:
if i[1][0] > i[1][1]:
target_file.write(" "+i[0]+" : OUT STD_LOGIC_VECTOR("+i[1][0]+" DOWNTO "+i[1][1]+")\n")
elif i[1][0] < i[1][1]:
target_file.write(" "+i[0]+" : OUT STD_LOGIC_VECTOR("+i[1][0]+" TO "+i[1][1]+")\n")
else:
raise ValueError("Wrong STD_LOGIC_VECTOR range")
else:
if i[1][0] > i[1][1]:
target_file.write(" "+i[0]+" : OUT STD_LOGIC_VECTOR("+i[1][0]+" DOWNTO "+i[1][1]+");\n")
elif i[1][0] < i[1][1]:
target_file.write(" "+i[0]+" : OUT STD_LOGIC_VECTOR("+i[1][0]+" TO "+i[1][1]+");\n")
else:
raise ValueError("Wrong STD_LOGIC_VECTOR range")
for i in outputs:
if i == outputs[-1]:
target_file.write(" "+i+" : OUT STD_LOGIC\n")
else:
target_file.write(" "+i+" : OUT STD_LOGIC;\n")
target_file.write(" );\n")
target_file.write(" END COMPONENT "+design_to_wrap.split(".")[0]+";\n")

def write_signals(target_file_name, signals_file_name):
with open(target_file_name, "a") as target_file, open(signals_file_name, "r") as signals_file:
for line in signals_file:
target_file.write(line)

def write_components_instantiation(target_file_name, components_instantiation_file_name, design_to_wrap, inputs, outputs, input_vectors, output_vectors):
with open(target_file_name, "a") as target_file, open(components_instantiation_file_name, "r") as components_instantiation_file:
for line in components_instantiation_file:
target_file.write(line)
target_file.write(" "+design_to_wrap.split(".")[0]+"_1 : "+design_to_wrap.split(".")[0]+"\n")
target_file.write(" PORT MAP (\n")
for i in inputs:
target_file.write(" "+i+" => "+i+",\n")
for i in input_vectors:
target_file.write(" "+i[0]+" => "+i[0]+",\n")
for i in output_vectors:
if outputs:
target_file.write(" "+i[0]+" => "+i[0]+",\n")
else:
if i != output_vectors[-1]:
target_file.write(" "+i[0]+" => "+i[0]+",\n")
else:
target_file.write(" "+i[0]+" => "+i[0]+"\n")
for i in outputs:
if i != outputs[-1]:
target_file.write(" "+i+" => "+i+",\n")
else:
target_file.write(" "+i+" => "+i+");\n\n")
def write_architecture_end(target_file_name):
with open(target_file_name, "a") as target_file:
target_file.write(" led_out_s <= ssi_start_transmit;\n")
target_file.write(" reset <= (NOT n_reset);\n")
target_file.write("\n")
target_file.write("END ARCHITECTURE rtl;\n")

def generate_wrapper(design_to_wrap, entity_name, target_file_name):

"""Wrapps a vhd design in a SALWARE wrapper"""

architecture_components_file_name = "architecture_components.txt"
signals_file_name = "signals.txt"
components_instantiation_file_name = "components_instantiation.txt"
if not os.path.isfile(architecture_components_file_name):
raise IOError("Architecture components file not found")
if not os.path.isfile(signals_file_name):
raise IOError("Signals file not found")
if not os.path.isfile(components_instantiation_file_name):
raise IOError("Components instantiation file not found")

inputs, outputs, input_vectors, output_vectors = identify_interface_signals(design_to_wrap)
write_header(target_file_name)
write_entity(entity_name,
target_file_name,
inputs,
outputs,
input_vectors,
output_vectors)
write_architecture_components(design_to_wrap,
entity_name,
target_file_name,
architecture_components_file_name,
inputs,
outputs,
input_vectors,
output_vectors)
write_signals(target_file_name, signals_file_name)
write_components_instantiation(target_file_name, components_instantiation_file_name, design_to_wrap, inputs, outputs, input_vectors, output_vectors)
write_architecture_end(target_file_name)
if __name__ == "__main__":
generate_wrapper("test.vhd", "top", "wrapper.vhd")