components_instantiation.txt 4 KB
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----------
-- Buffers
----------

n_reset_in_buffer : in_buf
PORT MAP (
PAD_IN(0) => n_reset_in,
Y(0) => n_reset
);

serial_in_buffer : in_buf
PORT MAP (
PAD_IN(0) => serial_in,
Y(0) => rx
);

MB_clk_in_buffer : in_buf
PORT MAP (
PAD_IN(0) => MB_clk_in,
Y(0) => MB_clk_s
);

ssi_clk_buf : clk_buf
PORT MAP (
CLK0 => MB_clk_s,
GL0 => ssi_clk,
LOCK => OPEN
);

serial_out_buf : out_buf
PORT MAP (
D(0) => tx,
PAD_OUT(0) => serial_out
);

led_out_buf : out_buf
PORT MAP (
D(0) => led_out_s,
PAD_OUT(0) => led_out
);

---------------------------
-- Components instantiation
---------------------------

ssi_inst : ssi
GENERIC MAP (
WIDTH => 64 -- Data bus width (MAX=511)
)
PORT MAP (
reset => reset, -- Positive reset
clk => ssi_clk, -- Input clock
data_in => ssi_data_to_transmit, -- Parallel data input (to be TX-ed)
load => ssi_start_transmit, -- Input data load (TX start)
rx => rx, -- RX serial line
data_out => ssi_data_received, -- Parallel data output (RX-ed data)
ready => ssi_data_received_ready, -- RX data ready
tx_empty => ssi_ready_to_transmit, -- TX buffer empty (ready to TX)
tx => tx -- TX serial line
);

TEROPUF : TEROPUF_core
PORT MAP (
clk => ssi_clk,
rst => rst_PUF,
ena => ena_PUF,
selec_in => TERO_index,
output_puf => output_puf,
strobe => PUF_data_ready);

controller_1 : controller
PORT MAP (
clk => ssi_clk,
rst_n => n_reset,
data_received_ssi => ssi_data_received,
data_received_ready => ssi_data_received_ready,
ssi_ready_to_transmit => ssi_ready_to_transmit,
PUF_data_ready => PUF_data_ready,
rst_PUF => rst_PUF,
ena_PUF => ena_PUF,
TERO_index => TERO_index,
ena_response_shift_register => ena_response_shift_register,
select_data_ssi => select_data_ssi,
send_data_ssi => ssi_start_transmit,
selected_PUF_bit_for_parity => PUF_response_bit_index,
ena_parity_computation => ena_parity_computation,
rst_n_sync_parity_module => rst_n_sync_parity,
ena_parity_shift_register => ena_parity_shift_register,
rst_parity_register => rst_parity_register);

response_shift_register : shift_register_2_bits
GENERIC MAP (
width => 128)
PORT MAP (
clk => ssi_clk,
rst_n => n_reset,
data_in => output_PUF,
ena => ena_response_shift_register,
data_out => PUF_response);

mux_data_to_ssi : mux4x64
PORT MAP (
data_in_0 => PUF_response(63 DOWNTO 0),
data_in_1 => PUF_response(127 DOWNTO 64),
data_in_2 => x"FFFFFFFF" & parity_register_value,
data_in_3 => x"0000000000000000",
selection => select_data_ssi,
data_out => ssi_data_to_transmit);

mux_response_bits_to_parity : mux_tero
GENERIC MAP (
WIDTH => 128,
SELECT_WIDTH => 7)
PORT MAP (
data_in => PUF_response,
selection => PUF_response_bit_index,
data_out => PUF_response_bit);

parity_computation_module : parity
PORT MAP (
clk => ssi_clk,
rst_n => n_reset,
rst_n_sync => rst_n_sync_parity,
data => PUF_response_bit,
ena => ena_parity_computation,
par => parity_value);

parity_shift_register : shift_register
GENERIC MAP (
width => 32)
PORT MAP (
clk => ssi_clk,
rst_n => rst_parity_register,
data_in => parity_value,
ena => ena_parity_shift_register,
data_out => parity_register_value);