architecture_components.txt 4.05 KB
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COMPONENT in_buf IS
PORT(
PAD_IN : IN STD_LOGIC_VECTOR(0 TO 0);
Y : OUT STD_LOGIC_VECTOR(0 TO 0)
);
END COMPONENT in_buf;

COMPONENT out_buf IS
PORT(
D : IN STD_LOGIC_VECTOR(0 TO 0);
PAD_OUT : OUT STD_LOGIC_VECTOR(0 TO 0)
);
END COMPONENT out_buf;

COMPONENT clk_buf IS
PORT(
CLK0 : IN STD_LOGIC;
GL0 : OUT STD_LOGIC;
LOCK : OUT STD_LOGIC
);
END COMPONENT clk_buf;

COMPONENT ssi IS
GENERIC (
WIDTH : INTEGER := 8 -- Data bus width (MAX=511)
);
PORT (
reset : IN STD_LOGIC; -- Positive reset
clk : IN STD_LOGIC; -- Input clock
data_in : IN STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0); -- Parallel data input (to be TX-ed)
load : IN STD_LOGIC; -- Input data load (TX start)
rx : IN STD_LOGIC; -- RX serial line
data_out : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0); -- Parallel data output (RX-ed data)
ready : OUT STD_LOGIC; -- RX data ready
tx_empty : OUT STD_LOGIC; -- TX buffer empty (ready to TX)
tx : OUT STD_LOGIC -- TX serial line
);
END COMPONENT ssi;

COMPONENT TEROPUF_core IS
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
ena : IN STD_LOGIC;
selec_in : IN STD_LOGIC_VECTOR(SEL_WIDTH-1 DOWNTO 0);
output_puf : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
strobe : OUT STD_LOGIC);
END COMPONENT TEROPUF_core;

COMPONENT controller IS
PORT (
clk : IN STD_LOGIC;
rst_n : IN STD_LOGIC;
data_received_ssi : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
data_received_ready : IN STD_LOGIC;
ssi_ready_to_transmit : IN STD_LOGIC;
PUF_data_ready : IN STD_LOGIC;
rst_PUF : OUT STD_LOGIC;
ena_PUF : OUT STD_LOGIC;
TERO_index : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
ena_response_shift_register : OUT STD_LOGIC;
select_data_ssi : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
send_data_SSI : OUT STD_LOGIC;
selected_PUF_bit_for_parity : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
ena_parity_computation : OUT STD_LOGIC;
rst_n_sync_parity_module : OUT STD_LOGIC;
ena_parity_shift_register : OUT STD_LOGIC;
rst_parity_register : OUT STD_LOGIC);
END COMPONENT controller;

COMPONENT shift_register_2_bits IS
GENERIC (
width : INTEGER);
PORT (
clk : IN STD_LOGIC;
rst_n : IN STD_LOGIC;
data_in : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
ena : IN STD_LOGIC;
data_out : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0));
END COMPONENT shift_register_2_bits;

COMPONENT mux4x64 IS
PORT (
data_in_0 : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
data_in_1 : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
data_in_2 : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
data_in_3 : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
selection : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
data_out : OUT STD_LOGIC_VECTOR(63 DOWNTO 0));
END COMPONENT mux4x64;

COMPONENT mux_tero IS
GENERIC (
WIDTH : INTEGER;
SELECT_WIDTH : INTEGER);
PORT (
data_in : IN STD_LOGIC_VECTOR(WIDTH - 1 DOWNTO 0);
selection : IN STD_LOGIC_VECTOR(SELECT_WIDTH - 1 DOWNTO 0);
data_out : OUT STD_LOGIC);
END COMPONENT mux_tero;

COMPONENT parity IS
PORT (
clk : IN STD_LOGIC;
rst_n : IN STD_LOGIC;
rst_n_sync : IN STD_LOGIC;
data : IN STD_LOGIC;
ena : IN STD_LOGIC;
par : OUT STD_LOGIC);
END COMPONENT parity;

COMPONENT shift_register IS
GENERIC (
width : INTEGER);
PORT (
clk : IN STD_LOGIC;
rst_n : IN STD_LOGIC;
data_in : IN STD_LOGIC;
ena : IN STD_LOGIC;
data_out : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0));
END COMPONENT shift_register;